(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming planarized shallow trench isolation in the fabrication of integrated circuits.
(2) Description of the Prior Art
Shallow trench isolation (STI) is gaining substantial interest for deep sub-micron processes. To achieve good planarity after STI, chemical mechanical polishing (CMP) is a more promising solution than is etchback. However, due to pad deformation, the trench open area is susceptible to dishing which causes oxide thinning in the wide trench. In addition, the pattern dependency of CMP leads to non-uniform oxide removal on the silicon nitride underlayer of different dimensions. In order to remove all the oxide on the silicon nitride before nitride stripping, overpolishing is generally carried out at the cost of severe oxide dishing and silicon nitride erosion.
FIG. 1 illustrates a partially completed integrated circuit device of the prior art. A pad oxide layer 12 and a silicon nitride layer 14 have been deposited over the surface of a semiconductor substrate 10. Trenches in the substrate have been filled with an oxide 17 which has been polished using CMP. Oxide dishing and silicon nitride erosion can both be seen in area 19.
In order to reduce these problems, the use of a reverse tone mask at the device pattern layer has been proposed. But, due to the great difficulties in overlaying the device pattern mask and reverse-tone device pattern mask on a non-planarized oxide surface, this approach becomes very challenging for deep sub-micron processes.
U.S. Pat. No. 5,275,965 to Manning shows a method of forming trench isolation using gated sidewalls. U.S. Pat. No. 5,494,857 to Cooperman et al teaches CMP shallow trenches using a reverse-tone mask and a silicon nitride polish stop layer. U.S. Pat. No. 5,518,950 to Ibok et al shows a method in which spin-on-glass in trenches is covered with a resist mask to increase the spin-on-glass thickness over the trenches.